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-- Company: 
-- Engineer: 
-- 
-- Create Date:    10:57:30 01/18/2014 
-- Design Name: 
-- Module Name:    steppermotor1 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;


-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity steppermotor is
    Port ( step_up,clk: in  STD_LOGIC;
           step_down : in  STD_LOGIC;
			  control_mode,step_mode :in std_logic;
           output : out  STD_LOGIC_VECTOR (3 downto 0));
			  
end steppermotor;

architecture Behavioral of steppermotor is
type my_state is (selection_mode , automatic_mode , manual_mode);
signal state : my_state:=selection_mode;

--type state_type is (stand_by,start,data,stop);
--signal state : state_type := stand_by;

signal cnt_manual_2bit , cnt_auto_2bit,cnt_2bit : std_logic_vector(1 downto 0);
signal cnt_auto_3bit , cnt_manual_3bit,cnt_3bit :std_logic_vector(2 downto 0);
signal out_full,out_half : std_logic_vector(3 downto 0);
signal en,new_up,clk_n: std_logic;
signal ce_auto_full,ce_manual_full,ce_auto_half,ce_manual_half : std_logic := '0';
signal mode : std_logic_vector(1 downto 0);


component stepper_manual_2bit IS
  PORT (
    clk : IN STD_LOGIC;
    up : IN STD_LOGIC;
	 ce : IN STD_LOGIC;
    q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
  );
END component;

component stepper_automatic_2bit IS
  PORT (
    clk : IN STD_LOGIC;
	 ce : IN STD_LOGIC;
    q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
  );
END component;
component stepper_manual_3bit IS
  PORT (
    clk : IN STD_LOGIC;
	 up : IN STD_LOGIC;
    ce : IN STD_LOGIC;
    q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
  );
END component;
component stepper_automatic_3bit IS
  PORT (
    clk : IN STD_LOGIC;
    ce : IN STD_LOGIC;
    q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
  );
END component;
begin
	
	en <= step_down xor step_up;
	mode(0) <= step_mode;
	mode(1) <= control_mode;
	
	u1: stepper_manual_2bit
		port map
		(
		clk => en,
		up => new_up,
		ce => ce_manual_full,
		q => cnt_manual_2bit		
		);
	
	u2: stepper_automatic_2bit
		port map
		(
		clk => clk_n,
		ce => ce_auto_full,
		q => cnt_auto_2bit
		);
	u3: stepper_manual_3bit
		port map
		(
		clk => en,
		up => new_up,
		ce => ce_manual_half,
		q => cnt_manual_3bit
		);
	u4: stepper_automatic_3bit
		port map
		(
		clk => clk_n,
		ce => ce_auto_half,
		q => cnt_auto_3bit
		);

--		output <= cnt;

		process(step_up,step_down)
		
		begin
			
			if(step_up = '0') then
				if(step_down = '0')then
					new_up <= step_down nor (not new_up);
				else
					new_up <= '0';
				end if;
			else
				if(step_down = '0') then
					new_up <= '1';
				else
					new_up <= not(step_down) nor (not new_up);
				end if;
			end if;
		end process;
		
		process(clk,control_mode)		
		variable ctr : std_logic_vector(23 downto 0);
		begin
		
			if(rising_edge(clk))then
				ctr := ctr + x"000001";		
				if(ctr = x"4C4B40") then
					clk_n <= not clk_n;
					ctr := x"000000";
				end if;
				case state is
					when selection_mode =>
						if(control_mode = '1')then
							state <= automatic_mode;
						else
							state <= manual_mode;
						end if;	
					when automatic_mode =>
						if(step_mode = '1')then
							output <= out_half;
							ce_manual_full <= '0';
							ce_manual_half <= '0';
							ce_auto_full <= '0';
							ce_auto_half <= '1';
						else
							output <= out_full;
							ce_manual_full <= '0';
							ce_manual_half <= '0';
							ce_auto_full <= '1';
							ce_auto_half <= '0';
						end if;
						state <= selection_mode;
					when manual_mode =>
						if(step_mode = '1')then
							output <= out_half;
							ce_manual_full <= '0';
							ce_manual_half <= '1';
							ce_auto_full <= '0';
							ce_auto_half <= '0';
						else
							output <= out_full;
							ce_manual_full <= '1';
							ce_manual_half <= '0';
							ce_auto_full <= '0';
							ce_auto_half <= '0';
						end if;
						state <= selection_mode;
					when others =>
				end case;

			end if;
			
		end process;
	
--	mode(0) <= step_mode;
--	mode(1) <= control_mode;
	process(mode)
	begin
		case mode is
			when "00" =>
				cnt_2bit <= cnt_manual_2bit;
			when "01" =>
				cnt_3bit <= cnt_manual_3bit;
			when "10" =>
				cnt_2bit <= cnt_auto_2bit;
			when "11" =>
				cnt_3bit <= cnt_auto_3bit;
			when others =>
				
		end case;
	end process;
	
	with cnt_2bit select
		out_full <=  "1100" when "00",
						 "0110" when "01",
						 "0011" when "10",
						 "1001" when "11",
						 "1111" when others;
--	output <= output2;
	with cnt_3bit select
		out_half <= "1000" when "000",
					 "1100" when "001",
					 "0100" when "010",
					 "0110" when "011",
					 "0010" when "100",
					 "0011" when "101",
					 "0001" when "110",
					 "1001" when "111",
					 "1111" when others;
					 
--	with cnt select
--		output <= "0001" when "00",
--					 "0010" when "01",
--					 "0100" when "10",
--					 "1000" when "11",
--					 "1111" when others;
	
--	process(cnt)
--	begin
--
--					case cnt is
--						when "00" => 
--							output <= "1100" ;
--						when "01" =>
--							output <="0110";
--						when "10" =>
--							output <="0011" ;
--						when "11" => 
--							output <="1001";
--						when others =>
--					end case;
--
--	
--	end process;
end Behavioral;